1. Field of the Invention
The present invention relates in general to an etching method. In particular, the present invention relates to a method of physical etching with a multilevel hard mask.
2. Description of the Related Art
In integrated circuit industries, conducting materials, semiconductors, and insulators are widely used, and thin film deposition, photolithography and etching are the main semiconductor techniques.
The above-mentioned materials are deposited by the technique of thin film deposition on a wafer layer by layer. The technique of photolithography is used to form patterns, and then the patterns are transferred to the layers to form elements, such as transistors or capacitors, or circuits.
With the advent of integration, the element structures and circuits are more and more complicated. In some cases, the material to be etched is not a simple material but a mass of multilayer materials. For example, in the structures of vertical transistors and underlying deep trench capacitors, performing shallow trench isolation is difficult. In this case, physical etching is chosen to pattern the structure to be etched with a BPSG layer (borophosphosilicate glass layer) as a consumptive mask. The thickness of the BPSP layer depends on the depth of the opening or trench to be formed. If the BPSG layer is too thick, it is difficult to transfer the pattern in the photoresist layer to the BPSG layer, and distortion of the pattern in the BPSG layer occurs easily. Therefore, it is difficult to form a deep opening or trench in these materials by physical etching.
The object of the present invention is to provide a multilevel hard mask as a consumptive mask, and the thickness of the multilevel hard mask is not limited by the limitations of the photoresist.
To achieve the above-mentioned object, the present invention provides a method for etching a multilayer structure using a multilevel hard mask. According to one aspect, a BPSG layer, a masking material layer and a patterned photoresist layer are sequentially formed on the multilayer structure. The pattern of the patterned photoresist layer is transferred to the masking material layer. The pattern of the masking material layer is then transferred to the BPSG layer by etching under the conditions of the high etching ratio of the BPSG layer to the masking material layer. The masking material layer and the BPSG layer functioning as a multilevel hard mask are used to physically etch the multilayer structure to form a trench therein.
In accordance with another aspect of the present invention, a method for forming a shallow trench isolation with a vertical transistor and a trench capacitor includes the following steps. A substrate with a layer to be etched which contains a trench capacitor, a vertical transistor, and possibly other circuit elements, is provided. A BPSG layer, a masking material layer and a patterned photoresist layer are sequentially formed on the layer to be etched. The pattern of the photoresist layer is transferred to the masking material layer. The pattern of the masking material layer is then transferred to the BPSG layer by etching under the conditions of the high etching ratio of the BPSG layer to the masking material layer. The masking material layer and the BPSG layer functioning as a multilevel hard mask are used to physically etch the layer to be etched to form a trench therein. An insulating material then fills the trench.